1. Field of the Invention
The present invention relates to a method of forming a device isolation trench, and particularly to a method of reducing crystal defects developed upon formation of shallow trench isolation (STI).
2. Description of the Related Art
A semiconductor device has constituent elements such as transistors, diodes, capacitors or resistors, etc. which are electrically separately arranged on a semiconductor substrate and interconnected with one another by wirings. A device isolation technique is the technique of principally physically isolating between these elements.
Upon device isolation, the planarization of the surface and simplification of a manufacturing process, or a possible reduction in device isolation width while a reduction in defect density is being performed, is desirable for the purpose of an improvement in device's characteristic, by extension, an increase in the performance of the semiconductor device and an improvement in its reliability.
The device isolation technique is roughly divided into LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation). The LOCOS method for selectively oxidizing the surface of a semiconductor substrate through an insulating film is accompanied by the problem that a device forming region is corroded due to bird beaks and crystal defects occur due to the occurrence of local stress at the formation of a field oxide film.
On the other hand, the STI method is advantageous to micro-fabrication or miniaturization. Described specifically, the present STI method is one wherein a trench is formed in a device isolation region by RIE (Reactive Ion Etching) or the like and thereafter an oxide film that serves as an embedding material is deposited by, for example, a CVD (Chemical Vapor Deposition) method, and the oxide film deposited on a portion other than the trench is removed and planarized using CMP (Chemical Mechanical Polishing) or the like, thereby performing device isolation.
An STI forming method according to a prior art will now be explained specifically with reference to FIGS. 1 through 3. A silicon oxide film 2 and a silicon nitride film 3 are sequentially formed over a silicon substrate 1 by thermal oxidation (see FIG. 1). The silicon oxide film 2 and the silicon substrate 1 are sequentially etched with the silicon nitride film 3 as a mask by using photolithography technology and a dry etching method to thereby form a trench 4 (see FIG. 2).
Thereafter, rounding oxidation for rounding the edges of the trench 4 is performed. A CVD oxide film 5 is embedded into the trench 4 and planarized by CMP technology. Then, the silicon nitride film 3 and the silicon oxide film 2 each used as a mask film are removed by thermal phosphoric acid and hydrofluoric acid respectively. The embedded CVD oxide film 5 is heat-treated to form an STI isolation region (see FIG. 3).
However, the heat-treatment employed in the conventional STI forming method aims to suppress the occurrence of divots caused by the occurrence of densification of the embedded oxide film 5. It was however understood that since the plane orientation of a normally used silicon substrate was (100), crystal defects with, particularly, an plane orientation (111) as the inception at a trench bottom would occur after trench processing.
As principal factors for the occurrence of the crystal defects, there are considered one caused by crystal damage due to ion implantation done unintentionally, and one caused by thermal stress developed through an oxidizing process, an activating process, and a heat-treating process like an annealing process in a state in which a difference in dense density occurs between the qualities of oxide films embedded in trenches.